Sundari, S. Bala Tripura: search on Z-Library

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1

[IEEE 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - Bangalore, India (2018.9.19-2018.9.22)] 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol

B, Vineeth, Bala Tripura Sundari, B.

Year:

2018

Language:

english

File:

PDF, 566 KB

english, 2018

2

A rapid and highly sensitive method for the determination of glimepiride in human plasma by liquid chromatography–electrospray ionization tandem mass spectrometry: application to a pre-clinical pharmacokinetic study

Lagishetty Chakradhar, Rajareddy Kallem, Arumugam Karthik, Bala Tripura Sundari, Srirangam Ramesh, Ramesh Mullangi, Nuggehally R. Srinivas

Journal:

Biomedical Chromatography

Year:

2008

Language:

english

File:

PDF, 202 KB

english, 2008

3

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) ||

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

File:

PDF, 2.16 MB

2003

4

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Switch Level Modeling

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 186 KB

english, 2003

5

A direct method for optimal VLSI realization of deeply nested n-D loop problems

Bala Tripura Sundari, B., Padmanabhan, T.R.

Journal:

Microprocessors and Microsystems

Year:

2013

Language:

english

File:

PDF, 3.54 MB

english, 2013

6

[IEEE 2014 International Conference on Devices, Circuits and Communications (ICDCCom) - Ranchi (2014.9.12-2014.9.13)] 2014 International Conference on Devices, Circuits and Communications (ICDCCom) - Two Rail-To-Rail Class-AB CMOS Buffers with High Performance Slew Rate and Delay

Sundari, Adipudi Bala Tripura, Srinivasulu, Avireni, Bhagirath, T. N.

Year:

2014

Language:

english

File:

PDF, 357 KB

english, 2014

7

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Introduction to VLSI Design

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 80 KB

english, 2003

8

[IEEE 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT) - Kollam, India (2017.4.20-2017.4.21)] 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT) - Modeling 15nm graphene FET with contact resistance effects using channel segmentation technique

Hariharan, S., Sundari, B. Bala Tripura

Year:

2017

Language:

english

File:

PDF, 538 KB

english, 2017

9

[IEEE 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) - Coimbatore, India (2014.3.6-2014.3.8)] 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) - Towards MuGFETs: A power reduction perspective

Sushmitha, A., Narthanaa, K., Aravindan, I., Kumar, A. S. Ajay, Sundari, B. Bala Tripura

Year:

2014

Language:

english

File:

PDF, 2.44 MB

english, 2014

10

Severe Gestational Hypothyroidism Increases BBB Nutrient Transport in the Offspring

Sundari, S. Bala Tripura, Raghunath, M.

Journal:

Nutritional Neuroscience

Year:

1999

Language:

english

File:

PDF, 1.58 MB

english, 1999

11

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Gate Level Modeling - 2

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 240 KB

english, 2003

12

[IEEE 2014 International Conference on Embedded Systems (ICES) - Coimbatore, India (2014.7.3-2014.7.5)] 2014 International Conference on Embedded Systems (ICES) - Allocation of optimal reconfigurable array using graph merging technique

Resmi, R., Tripura Sundari, B. Bala

Year:

2014

Language:

english

File:

PDF, 350 KB

english, 2014

13

Probable Basis of Altered BBB Nutrient Transport in the Offspring of Severely Hypothyroid Dams

Sundari, S. Bala Tripura, Rupalatha, M., Raghunath, M.

Journal:

Nutritional Neuroscience

Year:

1999

Language:

english

File:

PDF, 878 KB

english, 1999

14

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Behavioral Modeling II

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 236 KB

english, 2003

15

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || References

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 29 KB

english, 2003

16

High Level Synthesis for Retiming Stochastic VLSI Signal Processing Architectures

P N, Krishnapriya, Tripura Sundari, B. Bala

Journal:

Procedia Computer Science

Year:

2018

Language:

english

File:

PDF, 1.10 MB

english, 2018

17

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Index

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 44 KB

english, 2003

18

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Introduction to Verilog

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 135 KB

english, 2003

19

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Functions, Tasks, and User-Defined Primitives

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 152 KB

english, 2003

20

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Frontmatter

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 85 KB

english, 2003

21

[IEEE 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - Udupi (2017.9.13-2017.9.16)] 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI) - Fpga implementation of fourier segmentation for empirical wavelet transform

Pravin, N., Shishir, S. K., Anirudh, S., Srinath, R., Sundari, B. Bala Tripura

Year:

2017

Language:

english

File:

PDF, 362 KB

english, 2017

22

AIP Conference Proceedings [American Institute of Physics 5TH NATIONAL CONFERENCE ON THERMOPHYSICAL PROPERTIES: (NCTP‐09) - Baroda (India) (7–9 October 2009)] - Compact model for switching characteristics of graphene field effect transistor

Sreenath, R., Bala Tripura Sundari, B.

Year:

2010

Language:

english

File:

PDF, 902 KB

english, 2010

23

Simulation of carbon nanotube field effect transistors using NEGF

Aravind, S, Shravan, S, Shrijan, S, Sanjeev, R Venkat, Sundari, B Bala Tripura

Journal:

IOP Conference Series Materials Science and Engineering

Year:

2016

Language:

english

File:

PDF, 843 KB

english, 2016

24

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Appendix B

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 41 KB

english, 2003

25

[IEEE 2020 International Conference on Smart Electronics and Communication (ICOSEC) - Trichy, India (2020.9.10-2020.9.12)] 2020 International Conference on Smart Electronics and Communication (ICOSEC) - UVM based Controller Area Network Verification IP (VIP)

Goel, Abhinav, Sundari, B. Bala Tripura, Mathew, Sujith

Year:

2020

File:

PDF, 189 KB

2020

26

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) ||

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 2.16 MB

english, 2003

27

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Appendix A

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 38 KB

english, 2003

28

[IEEE 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT) - Kollam, India (2017.4.20-2017.4.21)] 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT) - Design of Tri-Gate Schottky Barrier Graphene Nanoribbon field effect transistor

Krishna, Kandrakota Madhu Sai, Sundari, B. Bala Tripura

Year:

2017

Language:

english

File:

PDF, 645 KB

english, 2017

29

DC, frequency characterization of Dual Gated Graphene FET (GFET) Compact Model and its Circuit Application - Doubler Circuit

Bala Tripura Sundari, B., Arya Raj, K

Journal:

IOP Conference Series Materials Science and Engineering

Year:

2017

Language:

english

File:

PDF, 849 KB

english, 2017

30

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || System Tasks, Functions, and Compiler Directives

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 272 KB

english, 2003

31

[IEEE 2019 International Conference on Communication and Electronics Systems (ICCES) - Coimbatore, India (2019.7.17-2019.7.19)] 2019 International Conference on Communication and Electronics Systems (ICCES) - Implementation of digital lattice filter using Schur Polynomial

Sivaramakrishnan, Sneha, Shunmugam, Swathika, Tripura Sundari, B. Bala

Year:

2019

File:

PDF, 2.17 MB

2019

32

[IEEE 2019 International Conference on Communication and Electronics Systems (ICCES) - Coimbatore, India (2019.7.17-2019.7.19)] 2019 International Conference on Communication and Electronics Systems (ICCES) - An Efficient Reconfigurable FIR Filter for Dynamic Filter order variation

Srinivasa Rao, Bandreddi Ray, Bala Tripura Sundari, B

Year:

2019

File:

PDF, 1.10 MB

2019

33

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Gate Level Modeling - 1

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 213 KB

english, 2003

34

Power Reduction by Clock Gating Technique

Srinivasan, Nandita, Prakash, Navamitha S., Shalakha D.,, Sivaranjani D.,, Sri Lakshmi G., Swetha, Sundari, B. Bala Tripura

Journal:

Procedia Technology

Year:

2015

Language:

english

File:

PDF, 164 KB

english, 2015

35

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Queues, PLAs, and FSMS

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 214 KB

english, 2003

36

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Modeling at Data Flow Level

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 194 KB

english, 2003

37

[IEEE 2017 IEEE 12th Nanotechnology Materials and Devices Conference (NMDC) - Singapore (2017.10.2-2017.10.4)] 2017 IEEE 12th Nanotechnology Materials and Devices Conference (NMDC) - Modeling graphene FET frequency doubler with integrated quantum capacitance effects using quartic equation technique

Hariharan, S., Sundari, B. Bala Tripura

Year:

2017

Language:

english

File:

PDF, 310 KB

english, 2017

38

Design Through Verilog HDL (Padmanabhan/Design Through Verilog HDL) || Behavioral Modeling - 1

Padmanabhan, T. R., Bala Tripura Sundari, B.

Year:

2003

Language:

english

File:

PDF, 297 KB

english, 2003

39

[IEEE 2018 Conference on Information and Communication Technology (CICT) - Jabalpur, India (2018.10.26-2018.10.28)] 2018 Conference on Information and Communication Technology (CICT) - Spectrum Sensing Using Windowed Kurtosis for Cognitive Radios

B, Anooja, Tripura Sundari, B Bala, P, Supriya

Year:

2018

Language:

english

File:

PDF, 272 KB

english, 2018

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